Computer Science/Computer Architecture

[์ปดํ“จํ„ฐ๊ตฌ์กฐ] Interrupt Cycle

์ดํƒœํ™ 2022. 10. 11. 20:32

๐Ÿค” ํ•ต์‹ฌ์ •๋ฆฌ

๊ณต๋ถ€๋ฅผ ํ•˜๋ฉฐ ํ•ต์‹ฌ์ด๋ผ๊ณ  ์ƒ๊ฐ๋˜๋Š” ๋ถ€๋ถ„์„ ๋ฝ‘์•„์„œ ์ •๋ฆฌํ•˜๊ฒ ์Šต๋‹ˆ๋‹ค.

 

6๋‹จ์›๊นŒ์ง€์˜ ํ•ต์‹ฌ์ •๋ฆฌ์ด๋ฉฐ ๋‹ค์Œ ๋‹จ์›์˜ ํ•ต์‹ฌ์ •๋ฆฌ๋Š” ๋‹ค์Œ ๊ธฐํšŒ์— ์ง„ํ–‰ํ•˜๊ฒ ์Šต๋‹ˆ๋‹ค.

 

์ปดํ“จํ„ฐ ๊ตฌ์กฐ๋ฅผ ๊ณต๋ถ€ํ•˜๋ฉฐ ํฌ์ŠคํŒ…์„ ํ•˜์ง€ ์•Š์•„ ์ดํ•ด๊ฐ€ ๋œ ๋˜์—ˆ๊ธฐ์— ํ‹€๋ฆฐ ๋ถ€๋ถ„์ด ์žˆ๋‹ค๋ฉด ์ง€์ ํ•ด์ฃผ์„ธ์š”!

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

๐Ÿ”Ž Interrupt Cycle

CPU๋Š” ์ˆœ์ฐจ์ ์ธ ๋ช…๋ น์–ด ์‹คํ–‰์„ ์ค‘๋‹จํ•˜๊ณ  ๋‹ค๋ฅธ ํ”„๋กœ๊ทธ๋žจ์„ ์ฒ˜๋ฆฌํ•  ์ˆ˜ ์žˆ๋„๋ก ํ•˜๋Š” ๋ฉ”์ปค๋‹ˆ์ฆ˜์„ ์žฌ์ œ๊ณต ํ•ด์ฃผ๋Š” ๊ฒƒ์„ interrupt๋ผ๊ณ  ํ•ฉ๋‹ˆ๋‹ค.

 

์ฃผ ํ”„๋กœ๊ทธ๋žจ์˜ ์ž…์žฅ์—์„œ ๋ณด๋ฉด ํ๋ฆ„์ด ๊นจ์ง€๊ธฐ ๋•Œ๋ฌธ์— ๋ฐฉํ•ด๋ฐ›๋Š”๋‹ค๊ณ  ํ‘œํ˜„ํ•œ ๊ฒƒ ๊ฐ™์Šต๋‹ˆ๋‹ค.

 

๋งŒ์•ฝ CPU๊ฐ€ ์–ด๋–ค ํ”„๋กœ๊ทธ๋žจ์„ ์ˆœ์ฐจ์ ์œผ๋กœ ์ˆ˜ํ–‰ํ•˜๋Š” ์ค‘์— ์™ธ๋ถ€๋กœ ๋ถ€ํ„ฐ ์ธํ„ฐ๋ŸฝํŠธ ์š”๊ตฌ๊ฐ€ ๋“ค์–ด์˜ค๊ฒŒ ๋˜๋ฉด, CPU๋Š” ์›๋ž˜ ํ”„๋กœ๊ทธ๋žจ์˜ ์ˆ˜ํ–‰์„ ์ค‘๋‹จํ•˜๊ณ , ์ธํ„ฐ๋ŸฝํŠธ๋ฅผ ๋จผ์ € ์ฒ˜๋ฆฌํ•ด์ค๋‹ˆ๋‹ค.

 

์ธํ„ฐ๋ŸฝํŠธ ์ฒ˜๋ฆฌ๊ฐ€ ๋๋‚˜๋ฉด ์›๋ž˜์˜ ํ”„๋กœ๊ทธ๋žจ์œผ๋กœ ๋ณต๊ท€ํ•˜์—ฌ ๊ทธ ์ˆ˜ํ–‰์„ ๊ณ„์†ํ•ฉ๋‹ˆ๋‹ค.

 

Interrupt Cycle์— ๋Œ€ํ•œ Micro Operation๊ณผ ์˜ˆ์‹œ๋ฅผ ํ†ตํ•œ ์ดํ•ด๋ฅผ ๋จผ์ € ์ง„ํ–‰ํ•˜๊ณ  Interrupt Cycle์— ๋Œ€ํ•œ flow chart๋ฅผ ํ†ตํ•ด ์ „์ฒด์ ์ธ ํ๋ฆ„์„ ํŒŒ์•…ํ•ด๋ณด๊ฒ ์Šต๋‹ˆ๋‹ค.

 

 

 

 

 

 

 

 

Micro Operation

Basic Computer๋Š” Instruction Cycle์„ ์‹คํ–‰ํ•˜๊ธฐ ์ „์— R์˜ ๊ฐ’์ด 0์ธ์ง€ 1์ธ์ง€ ํ™•์ธ์„ ํ†ตํ•ด Interrupt Cycle์„ ์‹คํ–‰ํ• ์ง€ ๋ง์ง€ ๋ฅผ ๊ฒฐ์ •ํ•ฉ๋‹ˆ๋‹ค.

 

๋งŒ์•ฝ $R=1$์ด๋ผ๋ฉด Interrupt Cycle์„ ์‹คํ–‰ํ•ฉ๋‹ˆ๋‹ค.

 

 

$RT_0$ Memory์˜ 0๋ฒˆ์จฐ ์ฃผ์†Œ๋Š” return address๋ฅผ ์‹คํ–‰ํ•˜๋Š” ๋ช…๋ น์–ด๋ฅผ ์ €์žฅํ•˜๋Š” ํŠน๋ณ„ํ•œ ๋ฒˆ์ง€๋กœ ๋‹ค์Œ ๋ช…๋ น์–ด๋ฅผ ์‹คํ–‰ํ•˜๊ธฐ ์œ„ํ•˜์—ฌ AR์„ 0์œผ๋กœ Clearํ•ฉ๋‹ˆ๋‹ค.

PC์˜ ๊ฐ’์ธ 256์ด next instruction์ด๋ฏ€๋กœ Temporary Register์ธ TR์— PC๋ฅผ ์ €์žฅํ•ฉ๋‹ˆ๋‹ค.

AR ← 0, TR ← PC
$RT_1$ 0๋ฒˆ์ง€์— ๋‹ค์Œ ์‹คํ–‰ํ•  ๋ช…๋ น์–ด๊ฐ€ ๋‹ด๊ธด ์ฃผ์†Œ์ธ TR์„ ์ €์žฅํ•ฉ๋‹ˆ๋‹ค.

PC๋ฅผ 0์œผ๋กœ Clearํ•ฉ๋‹ˆ๋‹ค.

AR ← TR, PC ← 0
$RT_2$ PC๋ฅผ 1 ์ฆ๊ฐ€์‹œ์ผœ BUN์„ ์‹คํ–‰ํ•ฉ๋‹ˆ๋‹ค.

์ดํ›„ Interrupt Cycle์„ ๋น ์ ธ๋‚˜๊ฐ€ I/O Program์„ ์‹คํ–‰ํ•ฉ๋‹ˆ๋‹ค.

Interrupt Cycle์„ ๋น ์ ธ๋‚˜๊ฐ”๊ธฐ ๋•Œ๋ฌธ์— IEN, R, SC๋ฅผ 0์œผ๋กœ Clearํ•ฉ๋‹ˆ๋‹ค.

PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0

 

 

 

 

 

 

 

 

 

 

 

 

Flow Chart Of Interrupt Cycle

 

Interrupt Cycle์˜ ์‹คํ–‰๊ณผ์ •์„ Flow Chart๋กœ ๊ทธ๋ฆฌ๋ฉด ์•„๋ž˜์™€ ๊ฐ™์Šต๋‹ˆ๋‹ค.

 

 

 

 

 

 

 

 

 

 

 

๋‹ค์Œ ํฌ์ŠคํŒ…์—์„œ๋Š” 2-pass assembler์˜ $1st$ pass ๋ฐ $2nd$ pass์—์„œ์˜ ๋™์ž‘์›๋ฆฌ๋ฅผ ์•Œ์•„๋ณด๊ฒ ์Šต๋‹ˆ๋‹ค.